Conventional semiconductor memory devices may use a memory structure characterized by a vertical stack of a tunnel oxide (SiO2), a polysilicon floating gate over the tunnel oxide, an intergate dielectric over the floating gate, and a control gate over the interlayer dielectric. The vertical stack may be formed on a crystalline silicon substrate. The substrate may include a channel region positioned below the vertical stack and source and drain on opposing sides of the channel region.
One particular type of flash memory cell structure is characterized by a vertical stack that includes an insulating oxide tunnel layer, a charge trapping nitride dielectric layer, an insulating top oxide layer, and a polysilicon control gate, all positioned on top of a crystalline silicon substrate.
In a typical operation, flash memory cells may be programmed by a hot electron injection process that injects electrons from the channel region to the nitride layer to create a negative charge within the nitride layer. The electron injection may be performed by applying a drain-to-source bias along with a high positive voltage on the control gate. The high voltage on the control gate inverts the channel region while the drain-to-source bias accelerates electrons towards the drain region. The electrons are generally accelerated towards the drain region, with some of the electrons being re-directed towards the bottom oxide layer. The accelerated electrons gain enough kinetic energy to cross the bottom oxide layer and enter the nitride layer. The nitride layer stores the injected electrons within traps and thus acts as a charge storing layer.
Once programmed, the charged nitride layer becomes a charge storage layer for the memory cell. The negatively charged charge storage layer causes the threshold voltage of the memory cell to increase, which changes the magnitude of the current flowing between the source and the drain at various control gate voltages. Reading the programmed, or non-programmed, state of the memory cell is based on the magnitude of the current flowing between the source and drain at a predetermined control gate voltage.
The programmed memory cell may eventually need to be erased. One typical erase mechanism is hot hole injection (HHI). In HHI, a negative voltage may be applied to the control gate and the source-to-well and drain-to-well interfaces may be reverse biased. The reverse bias generates hot holes that are attracted to the charge storage layer by the negative voltage applied to the control gate. This causes a net positive charge in the charge storage layer and reduces the threshold voltage of the device.
As semiconductor device feature sizes decrease, the thicknesses of the SiO2 layer, typically used as the intergate dielectric, decrease as well, resulting in the SiO2 layer approaching a thickness on the order of ten angstroms (Å). Unfortunately, thin SiO2 layers may break down when subjected to an electric field, particularly SiO2 layers having thicknesses less than 50 Å (5 nm) thick. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through such thin SiO2 layers by a quantum mechanical tunneling effect. In this manner, a leakage current may undesirably form between the control gate and the charge storage layer, adversely affecting the operability of the device. For example, the leakage current increases exponentially for about a two-fold decrease in thickness of a SiO2 layer. This exponential increase in the SiO2 layer leakage current can significantly affect the operation of semiconductor devices, particularly with regard to reliability and lifetime.